Akhil TV

Akhil TV is a Senior RTL/FPGA Design Engineer with over 5 years of experience specializing in Verilog/VHDL coding, RTL design, and unit-level verification. Currently serving as an ASIC Digital Design Staff Engineer at Synopsys Inc, Akhil previously worked at VVDN Technologies, where they designed an o-RAN Front-Haul Analyzer and developed AXI Stream RTL modules. Akhil holds a Bachelor of Technology in Electrical, Electronics, and Communications Engineering from Kannur University. They are also certified in VLSI Design and Verification from Sandeepani School of VLSI Design.