Anunay Bajaj is a seasoned professional specializing in scalable verification across chiplet and high-performance computing ecosystems. They possess extensive expertise in the technical evaluations and deployments of verification IPs, particularly in PCI Express and Compute Express Link subsystems. Currently serving as a Solutions Engineering Architect at Synopsys Inc, Anunay previously held the position of Sr. Principal Product Engineer at Cadence Design Systems and has led teams to align organizational needs with individual career growth. Anunay earned a Master’s degree in Software Systems from the Birla Institute of Technology and Science, Pilani, and a BTech in Electronics and Communications from Bharati Vidyapeeth's College of Engineering, Delhi.
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