Archit Katiyar is a Senior ASIC Digital Design Engineer at Synopsys Inc, with experience starting in December 2024. Prior to this role, Archit worked as an RTL Design Engineer II at Qbit Labs Private Limited from March 2021 to December 2024, where responsibilities included independent RTL coding for PCIe Gen 6 Exerciser. Archit previously served as an RTL Design R&D Engineer at KPIT from July 2019 to March 2021 and began career development as an Engineering Trainee. Archit holds a Bachelor of Technology in Electronics and Communication Engineering from Motilal Nehru National Institute of Technology, completed in 2019.
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