Bin Yu is a Senior ASIC Engineer at Synopsys Inc, where they focus on ASIC digital design as a Senior Staff Engineer. Previously, Bin held positions as a Senior ASIC Engineer at Ciena from 2021 to 2025 and as an ASIC/FPGA Engineer at Precise-ITC, Inc. from 2017 to 2021, developing verification plans and building verification environments. Bin started their career as a Layout Engineer at China Electronics Technology Group Corporation, contributing to high-speed PCB design and simulation from 2013 to 2015. Bin holds a Master's degree in Electrical and Electronics Engineering from the University of Windsor and a Bachelor of Engineering from Jiangnan University.
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