Cheng-Lian Yang is a Software Engineer at Synopsys, specializing in EDA tool development with a focus on hardware. Previously, Cheng-Lian worked as a Software Engineer II at 益華電腦 from 2019 to 2022, contributing to the Palladium Precompiler. Before that, they held the position of Staff Engineer at 新思科技 from 2023 to 2024 and served as a Senior R&D Engineer, focusing on Zebu Timing analysis. Cheng-Lian earned a Master of Science in Electronics Engineering from National Taiwan University in 2021 and a Bachelor's degree in Electrical, Electronic, and Communications Engineering Technology from 國立交通大學 in 2017.
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