Deepak Pandey

Deepak Pandey is a Senior Staff Engineer at Synopsys Inc, bringing around 10 years of industry experience in IP verification and development of verification IP. They have specialized in coverage-driven constrained random verification and have exposure to various on-chip bus architectures, including AMBA 5, ACE, and AXI. Deepak has developed chip-to-chip UCIe IP verification and has hands-on experience with leading simulators like Synopsys-VCS and IUS. They hold a Bachelor of Technology degree in Electrical and Electronics Engineering from the National Institute of Technology Tiruchirappalli.