Deepesh Srivastava

Deepesh Srivastava is currently a Standard Cell Layout Designer at Synopsys in Hyderabad and has experience in advanced technologies including 5nm, 7nm, and 180nm. They have designed various components such as level shifters and multi-bit flops, focusing on performance improvement and area minimization. Prior to Synopsys, Deepesh worked as a Principal Design Engineer at GlobalFoundries and has also held roles in ASIC design and layout training. Deepesh earned a Bachelor’s Degree in Electronics and Communications Engineering from Inderprastha Engineering College and completed a course in ASIC Design at Pine Training Academy.