Dhruv Jethi is a Senior Engineer specializing in ASIC Digital Design at Synopsys, with extensive expertise in the design and verification of mixed-signal IPs including PLLs and PWM. With over four and a half years of prior experience at NXP Semiconductors, they designed key digital blocks for advanced microchip projects and ensured their functionality through robust verification processes. Dhruv co-authored a paper on high-resolution pulse width modulation circuits, which was presented at notable conferences in 2022. Currently, they are pursuing a Master of Engineering in Electrical and Computer Engineering at the University of Waterloo. Dhruv is dedicated to continuous learning and excels in fast-paced environments, applying innovative solutions to complex challenges.
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