Dinakar B is an R&D Senior Engineer at Synopsys Inc since July 2022, having previously served as an R&D Engineer. Prior experience includes a position as a Student Intern at Epitome Circuits from March 2021 to July 2022. Dinakar B possesses strong knowledge of the basics of CMOS fabrication processes for MOSFETs and has designed a 12T standard cell library encompassing schematic and layout design, in addition to expertise in power, performance, area, and delay optimization. Key skills include LVS, DRC, antenna effect, latch-up, and IR drop analysis, along with an understanding of characterization flows for standard cells. Dinakar B holds a Bachelor of Engineering in Electronics and Communications Engineering from RNS Institute of Technology, completed in 2022, with mini-projects including an 8-bit modified booth multiplier, flash ADC, bandgap reference circuit, and 6T SRAM memory.
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