Harini Darapu

Harini Darapu is an ASIC Design Verification Engineer at Synopsys, currently involved in verifying a high-speed SerDes at 200Gb/s. Harini has previously worked as an Associate Digital Verification Engineer at Huawei, focusing on high-speed SerDes technologies, and as a Physical Design Engineer at MediaTek, where they contributed to various design aspects, including static timing analysis and signoff verification. Harini holds a Master’s degree in Electrical, Electronics, and Communications Engineering from Concordia University and a Bachelor’s degree in Electronics and Communications from Krishna University. They have hands-on experience in developing verification environments using SystemVerilog and UVM, along with expertise in functional verification techniques.