Jenifer Shiny

Jenifer Shiny is a Digital Design Staff Engineer with over 6 years of experience specializing in ASIC verification and SoC design integration. Currently working at Synopsys Inc, Jenifer has previously held roles at SmartDV Technologies and Ciena, where they developed various Video IPs, including SLVS-EC, SMPTE-SDI, and ARINC818. Proficient in Universal Verification Methodology (UVM), System Verilog, and various verification tools, Jenifer has demonstrated expertise in creating high data-rate VIPs, testbenches, and engaging directly with clients across multiple projects. Jenifer earned a Bachelor of Engineering in Electronics and Communications Engineering from Mepco Schlenk Engineering College in 2019.