Kapil Saxena is a Senior Staff Engineer specializing in ASIC Digital Design at Synopsys Inc, with a decade of VLSI RTL Design experience. They have previously held roles such as Senior Design Engineer at Mindlance Technologies and Technical Lead at UST, contributing to various aspects of architecture design, RTL integration, and debugging. Kapil earned a Bachelor of Technology in Electrical, Electronics and Communications Engineering from Punjab Technical University and is currently pursuing a High School Diploma in Science at Delhi Public School Ghaziabad Society.
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