MANJUNATH PATIL

Manjunath Patil is a Senior Staff Engineer and FPGA Prototyping and Emulation Application Engineer at Synopsys Inc, having previously served as a Manager I in Application Engineering. They have worked extensively on HAPS FPGA prototyping boards, ZEBU emulators, and various simulation flows, including VCS. Manjunath began their career with an internship at Synopsys Inc, focusing on digital design and verification using System Verilog. They hold an Engineer’s Degree in Electronics and Communications Engineering from Dayananda Sagar College of Engineering and a Master’s Degree in VLSI from Vellore Institute of Technology.