Meera Viswanath

Meera Viswanath is a Staff Engineer in R&D at Synopsys Inc, with experience dating back to January 2016, and previously held the title of Senior Software Engineer R&D. Meera specializes in design planning, multi-voltage low power design, UPF, power-aware synthesis, and ASIC design flow, contributing to the Synopsys Design Compiler/Fusion Compiler Team. Prior to the current role, Meera served as R&D Engineer II and completed a technical internship in the Design Group R&D at Synopsys in 2015. Educational qualifications include a Master's degree in Computer Engineering (VLSI Design) from the University of Cincinnati and a Bachelor's degree in Electronics and Communication Engineering from Amrita Vishwa Vidyapeetham. Additional studies were completed at Stanford Continuing Studies in 2018.