Parul Gangwar is a Staff Engineer at Synopsys Inc, where they design new methodologies and flows for embedded memory circuit design. They previously held roles as a Technical Intern at Synopsys Inc and an Intern at STMicroelectronics. Parul has experience in memory circuit design and scripting with TCL and bash. They earned a Master of Technology (M.Tech) in VLSI from the Vellore Institute of Technology, graduating with a GPA of 9.03.
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