Raushan Pandit

Raushan Pandit is currently a Staff Engineer at Synopsys Inc, contributing expertise in digital design and verification. With a strong background in the semiconductors industry, they have honed skills in Universal Verification Methodology (UVM), SystemVerilog, and RTL Verification. Raushan holds a Bachelor of Technology in Electrical, Electronics and Communications Engineering from K N S Institute of Technology, and previously gained practical experience through roles as a Design Verification Engineer at several companies, including NXP Semiconductors and Smartiops. Prior to these positions, Raushan completed a Diploma in Electronics and Communications Engineering from Madhyamanchal Regional Engineering College, Nepal.