Sanjay Menon is a Senior Research and Development Engineer at Synopsys, where they are currently contributing to advanced projects in the field of RISCV technology. With a Bachelor of Technology in Electrical, Electronics, and Communications Engineering from Model Engineering College, they previously served as a CPU Validation Engineer at Valtrix Systems, focusing on the flagship tool STING for Design Verification. Sanjay also has experience as a Physical Design Engineer at Open-Silicon, where they worked with various chip design technologies and automation tools.
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