Sreeram k

Sreeram K is an Asic Digital Design Staff Engineer at Synopsys, with previous experience as an RTL Engineer at Intel Corporation. Their expertise includes design and verification, specifically in coding and verifying common debug signals architecture in System Verilog, as well as RTL power estimation using the Power Artist Tool. They hold a Master of Technology in Electronics Design and Technology from the National Institute of Technology Calicut and are currently pursuing a Bachelor of Technology in Electronics and Communications Engineering at RGUKT IIIT Nuzvid. Sreeram K is a result-oriented and self-driven professional, eager to learn new technologies and methodologies in the field.