Sudeshna Sarkar

Sudeshna Sarkar is an R&D Technical Manager at Synopsys Inc., where they lead efforts in layout design within the EDA R&D team. With ten years of experience in the semiconductor industry, Sudeshna previously served as a Senior Staff Physical Verification Lead at Samsung Semiconductor and gained early experience as an Assistant Professor at Poornima Foundation and an intern at STMicroelectronics. Sudeshna holds a Master of Technology in VLSI Design from Banasthali University and a Bachelor of Technology in Electronics and Communication from Rajasthan Technical University. Their technical expertise encompasses physical verification, product validation, and flow methodology across various design technologies.