Tejaswini Saini is a staff engineer in R&D engineering at Synopsys Inc, where they have contributed to memory design since 2020. Prior to this role, they served as an R&D Engineer II at the same company, beginning in 2024, and previously held the position of R&D Engineer I. Tejaswini earned a Bachelor of Engineering in Electrical, Electronics, and Communications Engineering from Netaji Subhas Institute of Technology from 2015 to 2019.
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