Veena P.

Veena P. is an experienced ASIC verification engineer with 7 years in the VLSI industry, currently working at Synopsys Inc. as a Digital Design Staff Engineer focusing on DDR-PHY verification. Veena previously served as a Senior Verification Engineer at Ignitarium, where they gained expertise in creating verification environments and protocols. Veena began their career as a trainee at Sandeepani School of VLSI Design, having completed a Professional Development Course in VLSI Design and Verification. They hold a Master of Technology in Micro & Nanoelectronics from the College of Engineering Trivandrum and a Bachelor of Technology in Applied Electronics and Instrumentation from Government Engineering College, Kozhikode.