Vineet Dubey

Vineet Dubey is a Staff Engineer specializing in ASIC Digital Design Methodology at Synopsys and previously worked as a CAD Engineer at Intel. They hold a Master of Technology in Integrated Circuit Technology from the University of Hyderabad, where they focused on digital circuit design and microelectronics. With hands-on experience in RTL design, static timing analysis, and FPGA flow, Vineet has also created a verification environment using SystemVerilog for their master's thesis. Their early career included internships at Synopsys and Unistring Tech Solutions, as well as involvement in robotics projects with DINOBOTS.