Vivek Gaur is a seasoned professional in the field of electronic design automation, currently serving as Group Director R&D at Synopsys since July 2012. In this role, Vivek oversees Parallel Simulation, Simulation Performance, and Core Simulation for the industry-leading logic simulator VCS, with a focus on improving design development and verification through incremental compilation technologies. Prior to this, Vivek held the position of Sr Staff R&D Engineer at Synopsys from 2001 to 2012, concentrating on simulation performance and compilation techniques. Vivek started the career as an EDA System Software Engineer at Compaq Computer from 1999 to 2001. Educational credentials include a Master of Science in Electrical and Computer Engineering from Northeastern University and a Bachelor of Technology in Computer Science from IET Lucknow.
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