Vivek Uppal is the Sr Director of R&D at Synopsys Inc, where they lead a team of ASIC Digital Design Engineers focused on Serdes IPs for various serial link standards. With over 15 years of prior experience in Serial Link PHYs and CMOS technologies, Vivek has developed expertise in PHY IP specifications, architecture decisions, and validation strategies. They hold a Bachelor of Engineering in Electronics & Communication from Delhi College of Engineering, obtained in 2000.
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