Wayne Lim is a Principal Architect specializing in AI/ML for Electronic Design Automation (EDA) and semiconductor modeling and design analytics. They have directed machine learning initiatives at Cadence and led AI/ML efforts at Synopsys Inc, where they developed technical roadmaps to enhance design performance. With experience as a Modeling Engineer and Senior Modeling Engineer at Silvaco Inc, Wayne contributed to improved predictive capabilities in design tools. Currently, they are pursuing a Master of Science in Electrical and Computer Engineering at UCSB College of Engineering.
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