Joseph Martinez

Joseph Martinez has worked in the engineering field since 1997. Joseph began their career as an FPGA Applications Engineer/FPGA Software Engineer Intern at Atmel Corporation. During their time there, they developed the company's FPGA flagship product family AT40K, creating, designing and simulating test suites for all AT40K products. In 1999, they joined S3 Graphics as a Member of Technical Staff, developing mobile graphics chipsets such as SavageMX, AlphaChrome and DeltaChrome. In 2005, they returned to Atmel Corporation as a Senior Design Engineer, taking ownership of several digital peripheral IP projects and being responsible for the digital verification for all LP product families. From 2017 to 2022, they worked at GSI Technology as a Member of Technical Staff, responsible for development and maintenance of DFT insertion, Formality checking and TetraMAX pattern generation. Joseph also worked at Xilinx as a Senior Design Engineer (Contractor with Triple Crown Consulting), where they were responsible for the design integration role for the low power domain. Currently, they are an RTL Design Engineer at TenaFe Inc.

Joseph Martinez attended San Jose State University from 1991 to 1997, where they earned a Bachelor of Science in Computer Engineering.