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Djordje Maksimovic
Principal Engineer
Brian Chen
Senior CPU Engineer
Sofija Jovic
Senior Software Engineer
Victor Ying
Senior Engineer, Future-gen Risc-v CPU Architecture
Zlatomir Pošarac
Senior System Engineer
Staff Engineer, CPU Core Feature Verification And Debug
Vacant position
CPU Core Feature Verification And Debug Engineer
CPU RTL Engineer, Shared Cache
November, 2023 - present
Senior CPU Engineer at Codasip