Adiveppa J is a seasoned Layout Engineer currently serving as a Sr. Design Engineer in Analog Design and PDK Development at Tessolve since 2024. With a robust background in the semiconductor industry, Adiveppa has previously worked as an Analog Layout Engineer at Sankalp Semiconductor and HCLTech from 2021 to 2024, and as a Layout Engineer at KarMic Design Private Ltd from 2017 to 2021. A strong engineering professional, Adiveppa graduated from LET College Gokaka, where they continue to advance their education.
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