Santosh Matagar

Santosh Matagar is a seasoned engineer with extensive experience in ASIC design verification and project management. Currently serving as a Staff Engineer at Tessolve since October 2020, Santosh previously held roles as Senior Design Lead Engineer and Lead Engineer at Altran from January 2019 to September 2020. Prior experience includes a position as Senior Verification Engineer at SmartPlay Technologies from September 2015 to December 2018 and VLSI Design & Verification Engineer at Wipro Technologies between June 2011 and August 2015. Santosh possesses a strong background in IP-level front-end verification, with expertise in SystemVerilog, OVM, and PCIe protocols. Santosh earned a Bachelor of Engineering in Electronics and Communication from VTU Belgaum in 2010.