Shajeer K

Shajeer K is a Senior Design Engineer at Test and Verification Solutions since July 2019, and also serves as a Lead Engineer at Quest Global Japan. With over 9 years of experience in VLSI digital design and verification, Shajeer has expertise in aerospace verification engineering, test case preparation, and the verification of top-level and block-level designs. Additional experience includes roles as a Senior Engineer at PerfectVIPs and as a VLSI Designer at Mutech Infotracks. Prior positions include Design Manager at Aspire Technologies, where Shajeer designed communication protocols using VHDL and Verilog for FPGA. Academic qualifications include an M.Sc in Electronics from MG University, a B.Sc in Electronics from National College, and specialized training in System Verilog verification from Maven Silicon.