TH

Takashi Hirano

Hardware Design Engineer at Tier IV

Takashi Hirano has extensive work experience in the field of hardware design and engineering. Takashi currently works at TIER IV as a Hardware Design Engineer since October 2022. Prior to joining TIER IV, Takashi worked at AMD as a Senior System Design Specialist from February 2022 to September 2022. Before that, they worked at Xilinx as a System Design Specialist from December 2021 to February 2022.

Takashi's earlier work experience includes a long tenure at Digitite, where they served as Representative Director from August 2009 to December 2021. During this time, they led the development of various projects, including an FPGA-based image processing system and a DMA controller for medical equipment.

Takashi also worked at Olympus Digital System Design as the Deputy General Manager from May 2007 to July 2009, where they promoted an ASIC project and conducted evaluations of high-level synthesis tools for image processing.

In addition, Takashi worked at AOI Technology as a Senior Engineer from November 2003 to April 2007, leading the development of ASIPs and conducting evaluations of bus architectures for ASICs. Takashi started their career at Fujitsu as a Design Engineer from February 2000 to November 2003, focusing on digital audio circuits and firmware development.

Before joining Fujitsu, Takashi worked at Agilent Technologies as an R&D Engineer from November 1999 to January 2000. Takashi also gained experience at Hewlett-Packard Japan, Ltd. as an R&D Engineer from July 1997 to November 1999 and at Texas Instruments as an Application Engineer from April 1994 to May 1997.

Overall, Takashi Hirano has a diverse range of experience in hardware design and engineering, with expertise in FPGA-based systems, image processing, ASIC development, and firmware development.

Takashi Hirano completed their high school education at Fukuyama Nishi High School in Hiroshima Prefecture, Japan from 1985 to 1988. Following this, they pursued a Bachelor's Degree in Electrical and Electronics Engineering at the Tokyo Institute of Technology from 1988 to 1993.

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  • Hardware Design Engineer

    October, 2022 - present