Stephen Nease

Stephen Nease is an experienced professional in ASIC design with a strong background in electrical and electronics engineering. Currently serving as Manager and previously as Principal and Senior ASIC Design Engineer at Tokyo Electron US since August 2020, Nease has extensive experience in designing and testing mixed-signal circuits, including neuromorphic systems and field-programmable analog arrays (FPAAs) from roles at TSMC and Ambiq Micro. With a Ph.D. from Georgia Institute of Technology, Nease's academic contributions include notable projects in neuromorphic circuits and VLSI chip design, complemented by experiences at Boston Scientific and Pacer Digital Systems as an intern.