Vahe Yeghiazaryan

Vahe Yeghiazaryan is an experienced engineering manager and ASIC physical design engineer with a background in leading physical design teams and managing full ASIC physical implementation processes. At Cisco from May 2017 to October 2020, Vahe served as an Engineering Manager responsible for project planning, scheduling, and providing technical support through all phases of ASIC design, including synthesis, formal verification, and signoff checks. Prior to Cisco, from July 2012 to May 2017, Vahe worked at Synopsys, where responsibilities included PnR technology file creation, logic library validation, and development of custom flow for advanced nodes, contributing to the design of logic library test chips and subblock structures.