Jui-Ping Chiang

Jui-Ping Chiang is a Principal Engineer at TSMC, with extensive experience since November 2009 in developing and maintaining Programmable ERC techfiles for ESD and latch-up protection checks, collaborating with ESD experts and tool vendors to enhance verification processes. Previous roles at TSMC include Senior Engineer positions focused on design verification techfiles, high-voltage ESD protection designs, and wafer-level testing. Early experience includes work as a Semiconductor Engineer designing test patterns and supporting BCD process development. Jui-Ping's academic background includes a Master of Science in Electrical and Computer Engineering from the University of Maryland and a Bachelor of Science in Physics from National Taiwan University. Additionally, research as a Graduate Research Assistant involved developing carbon nanotube transistors for biosensing applications.