Michal Lewandowski

Michal Lewandowski has extensive experience in the field of analog IC engineering, specializing in high-speed wireline digital serial links and power management sub blocks. Michal began their career in 2001 as a Junior Designer/Tester at Alatek, where they were responsible for hardware and software testing of Verilog/VHDL verification solutions. In 2002, they joined Chipidea as an Analog IC R&D Engineer, where they played a crucial role in the design and validation of high-speed wireline digital serial links and power management sub blocks. From 2007 to 2009, they worked at MIPS Technologies as an IC R&D Engineer/Group Leader, leading the design of analog ICs for high-speed wireline digital serial links. Michal then joined Synopsys, where they worked from 2009 to 2022 as an IC R&D Engineer/Group Leader, primarily focusing on designing PHYs for various protocols in IC technologies from TSMC, UMC, and SMIC. In addition to their work on front-end design, Michal also contributed to power management, clock generation, signal integrity, control theory, analog blocks, and ESD/latchup issues. In 2022, they joined Universal Quantum as an IC R&D Engineer, contributing their expertise to the development of quantum technology.

Michal Lewandowski attended Gdańsk University of Technology from 1997 to 2002, where they completed a Master of Science (MSc) degree in Electrical, Electronics and Communications Engineering.