Untether AI
Saijagan has three years of work experience. From 2019 to present, Saijagan has been an IC Design Engineer at Untether AI. From 2017 to 2019, Saijagan was a Project Associate (Analog & RF Design and Layout Engineer) at the Indian Institute of Science (IISc). In this role, Saijagan's key tasks included designing a Superheterodyne Receiver, LO Generation block, and PA Driver block, as well as delivering floorplan and pin arrangement activities. From 2015 to 2017, Saijagan was a student at Carleton University.
Saijagan completed a Bachelor of Engineering (B.E.) in Electrical, Electronics and Communications Engineering from Sri Siddhartha Institute of Technology between 2010 and 2014. Saijagan then went on to pursue a Master of Engineering (MEng) in Electrical and Electronics Engineering at Carleton University from 2015 to 2017. Prior to that, Saijagan attended NEW BALDWIN INTERNATIONAL SCHOOL from 2006 to 2008.