Victor Barsoum

Victor Barsoum has a strong background in engineering and verification roles. Victor is currently working as a Senior Verification Engineer at Untether AI, where they are responsible for integrating Register Abstraction Layer (RAL) models and developing simulation infrastructure. Prior to this, they worked at AMD as a Senior Silicon Design Engineer, focusing on verifying multiple AXI based blocks. Victor also has experience as a Senior ASIC Design Engineer at Vishare Technology Ltd, where they designed a deblocking filter. Victor has worked as an ASIC Design Engineer at ASTRI, where they implemented a SystemVerilog Verification Environment. Victor began their career as a Research Assistant at HKUST, working on MIMO OFDM Receiver/Transmitter modules. Before that, they worked as a Modelsim QA Engineer at Mentor Graphics and as an Electronics Engineer at Pyramid Systems Development.

Victor Barsoum completed a Master's degree in Integrated Circuits Design Engineering at The Hong Kong University of Science and Technology. No specific dates were provided for their education at this institution.