Piotr Paszkowski is an experienced engineer specializing in ASIC and FPGA design and verification. Currently serving as an ASIC/FPGA Staff Design Engineer and Team Leader at Vtool - Smart Verification since April 2025, Piotr has previously held significant positions such as Staff Design Verification Engineer at Analog Devices from July 2021 to March 2025 and FPGA/DSP Designer at Nokia from August 2013 to June 2021. Prior roles include FPGA Designer at Woodward Inc. and FPGA/ASIC Engineer at Motorola Mobility. Piotr also has experience as an ASIC Engineer at Evatronix. Piotr Paszkowski holds a Master’s degree in Electronics and Telecommunications from Poznan University of Technology, earned between 2003 and 2008.
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