Sarath K S

Senior Fpga/rtl Design Engineer at VVDN Technologies

Sarath K S is a Senior FPGA/RTL Design Engineer at VVDN Technologies, serving since September 2018. Prior to this role, Sarath contributed as an FPGA/RTL Design Engineer at ISRO from September 2016 to February 2017. Sarath holds a Bachelor's degree in Electrical, Electronics and Communications Engineering from Nehru College of Engineering and Research Centre, completed in 2017. Additionally, Sarath participated in the SAP Student Academy Program during 2016-2017 and completed secondary education at GHSS Pattambi and TRK HSS Vaniamkulam.

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VVDN Technologies

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VVDN has more than a decade of experience in Product Engineering & Manufacturing electronic solutions. VVDN Technologies helps customers steer their next-generation solutions with end-to-end design, development, and manufacturing – all under one roof.


Headquarters

Gurugram, India

Employees

1,001-5,000

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