Sarath K S

Sarath K S is a Senior FPGA/RTL Design Engineer at VVDN Technologies, serving since September 2018. Prior to this role, Sarath contributed as an FPGA/RTL Design Engineer at ISRO from September 2016 to February 2017. Sarath holds a Bachelor's degree in Electrical, Electronics and Communications Engineering from Nehru College of Engineering and Research Centre, completed in 2017. Additionally, Sarath participated in the SAP Student Academy Program during 2016-2017 and completed secondary education at GHSS Pattambi and TRK HSS Vaniamkulam.