Tse-Chen Yeh

Tse-Chen Yeh is a Principal Engineer at Western Digital since November 2017, specializing in virtual platform development, ASIC functional block modeling, virtual platform integration, and testcase creation. Prior to this, Tse-Chen served as a Senior Verification Engineer at Metanoia Communications Inc. from January 2014 to November 2017, focusing on DSP processor modeling for Motorola 56K. Tse-Chen also worked as a Research Assistant at the Institute of Information Science, Academia Sinica, from April 2011 to December 2013, addressing research issues related to cloud computing. Tse-Chen holds an All But Dissertation (ABD) PhD candidate status in Computer Science and Engineering from National Sun Yat-sen University (2002-2011) and a Master's degree in Computer Science and Engineering from I-Shou University (2000-2002).