Aditya Hendra is a Senior ASIC Verification Engineer at ZeroPoint Technologies, having previously held positions at Axis Communications, where they specialized in coverage-driven constraint random verification and module-level verification. Aditya's career began at PT. Datindo Infonet Prima as a Software Quality Lead, followed by roles as a Software Testing Engineer at Oberthur Technologies and a Master Thesis researcher at ABB. Aditya holds a Bachelor's degree in Computer Science and Mathematics from Universitas Bina Nusantara and a Master's degree in Embedded Systems from Uppsala University.
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