Prajwal Bhat

Prajwal Bhat is an experienced professional in the field of electrical and electronics engineering, currently serving as an ASIC Physical Design Engineer at Abacus Semiconductor Corporation since February 2025. Previous roles include working at Intel Corporation in a full-time position focusing on CAD RV Methodology from January 2024 to February 2025, and serving as a Physical Design Engineer at Cirrus Logic, where responsibilities encompassed block-level implementation from synthesis to static timing analysis. Additional experience includes a graduate student assistant role at Arizona State University and a tenure as a Physical Layout Design Engineer at Insemi Technology Services Pvt. Ltd., specializing in block-level implementation of SRAM and analog layouts. Prajwal Bhat holds a Master of Science degree in Electrical and Electronics Engineering from Arizona State University, completed in December 2023, and has a background in engineering education from Visvesvaraya Technological University.