Harry Vado

Harry Vado has over 20 years of experience in the field of FPGA engineering. Harry began their career in 1997 as a Senior IC Design Engineer and IC Design Development Engineer at Philips Semiconductors. In 2003, they took on the role of HW Technical Lead for IC Validation at NXP Semiconductors. In 2008, they worked as a Contract Senior Design Engineer at HDL Design House. From 2009 to 2018, they were a Principal Electronic Design Engineer at Airbus Defence and Space, where they were responsible for detailed RTL design, verification and synthesis, I/O constraints, Place and route, timing closure and power estimation for FPGA solutions, DfT, pad ring design, post layout STA and test oriented simulations for ASIC solutions. From 2014 to 2016, they were an FPGA Engineer at Nexsan. Harry also worked as a Contract FPGA Engineer at AIRBUS DEFENCE AND SPACE LIMITED from 2018 to 2019 and at OCZ Storage Solutions - A Toshiba Group Company from 2016 to 2018. In 2018, they also worked as a Contract FPGA Engineer for AccelerComm Ltd, where they participated in the design of FEC encoder and decoder IPs and submodules RTL design, simulation and synthesis. Since 2019, they have been a Principal FPGA engineer at AccelerComm Ltd.

Harry Vado obtained a Master's degree in Electrical and Electronics Engineering from Ecole Polytechnique de l'université de Nantes in 1900.