Padmavathi Alakunta

Padmavathi Alakunta is a Senior Design Verification Engineer at ACL Digital, currently contracted with AMD. With four years of experience, Padmavathi has expertise in IP-level verification, utilizing System Verilog and UVM methodology. They have developed testbenches and created detailed test plans and diverse test cases, while also gaining proficiency in code and functional coverage analysis. Previously, Padmavathi worked as a Trainee at VLSI FIRST and as a Design Verification Engineer at Tech Mahindra, where they implemented test cases and developed assertions.