Yashwanth Dandu

Yashwanth Dandu is a skilled Layout Design Engineer currently working at ACL Digital since March 2023, focusing on UMC 22nm Compilers and previously on DBHitek 180x Compilers. Prior experience includes serving as a Layout Engineer at Insemi Technology Services Pvt. Ltd. from March 2022 to February 2023, where Yashwanth contributed to the development of SRAM 10nm Control blocks and designed standard cell layouts in 22nm, 14nm, and 10nm using FINFET technology. An earlier internship at the Indian Institute of Remote Sensing (IIRS) under ISRO involved participation in projects related to Remote Sensing, GIS, and GNSS from July 2021 to December 2021. Yashwanth holds a Bachelor's degree in Electronics and Communications Engineering from Jawaharlal Nehru Technological University Anantapur, earned in June 2022.