Jose Sandoval

Jose Sandoval is an experienced FPGA Engineer currently employed at Adtran since January 2023, focusing on FPGA, CPLD, and verification methodologies such as OVM and UVM. Previously, Jose held the position of Senior FPGA Designer at ADVA Optical Networking from January 2011 to May 2023, specializing in RTL design and verification. Additional experience includes roles at De La Rue North America, Crane Aerospace & Electronics, Brocade, Tellabs, and 3Com, spanning over two decades in electrical engineering and hardware design. Jose holds a Bachelor of Science in Electrical Engineering from the University of Silicon Valley, obtained in 1993.