Archana Rengaraj

Archana Rengaraj is an experienced engineer in silicon design and verification, currently serving as an MTS Silicon Design Engineer at AMD, focusing on Infinity Fabric Verification since September 2025. Prior to this role, Archana worked at Intel Corporation as an IP Design Verification Engineer for a brief period and previously held various roles at Intel, including Sr. Pre-Silicon IP Verification Engineer, leading the verification of Boot Logic IP using UVM, and Sr. Soc Pre-Silicon Power Management Verification Engineer. Experience also includes positions at Cornelis Networks as an ASIC Verification Engineer and early roles at Synopsys Inc as a Verification Intern. Archana holds a Master's degree in Electrical & Computer Engineering from the University of Massachusetts Amherst and a Bachelor's degree in Electrical & Electronics Engineering from SSN College of Engineering, Anna University.