Revanth Chakilam

Revanth Chakilam is a CAD/Methodology and Layout Design Engineer at Ampere since August 2022, with experience in high-speed block physical design, ASIC design flow, and timing convergence strategies. Prior experience includes roles as an AMS Layout Design Engineer at INVECAS and an Analog Layout Trainee at VEDA IIT, focusing on Analog and Mixed Signal IC Layout Design across various technology nodes such as 14nm FinFet and 28nm MOSFET. Revanth also worked as an Engineer at Tata Elxsi. Education includes a Master of Science in Electrical and Computer Engineering from Portland State University and a Bachelor of Technology in Electronics and Communication Engineering from the Institute of Aeronautical Engineering.