Jatin Nagpal

Jatin Nagpal is a Senior Design Verification Engineer at Analog Devices, where the focus is on establishing Simulation Acceleration and In Circuit Emulation flow for an Arm-based Processing Platform since March 2021. Previously, Jatin served as a Senior R&D Engineer I at Synopsys Inc. from July 2012 to March 2021, specializing in the development of a Transactor for emulation platforms using Verilog and C++. Jatin's earlier role at Synopsys included responsibilities in validation and quality monitoring of the VCS software tool, with a focus on various hardware description languages and verification methodologies. Jatin started in the industry as an intern at Mentor Graphics, gaining hands-on experience in design and verification using System Verilog. Jatin holds a Master of Science in Data Sciences and Engineering from BITS Pilani and a Bachelor of Engineering in Electronics and Communication from Delhi College of Engineering.