Arteris
Guillaume Boillet has extensive work experience in the field of product management and marketing. Guillaume is currently employed at Arteris as the Sr. Director of Product Management & Strategic Marketing, a role they started in April 2022. Prior to this, they held the position of Sr. Director of Product Management at Arteris from January 2022 to March 2022, and Director of Product Management from November 2020 to December 2021.
Before joining Arteris, Guillaume worked at Synopsys Inc as a Sr. Product Marketing Manager from March 2018 to November 2020. Guillaume was responsible for product marketing activities during their tenure.
Prior to Synopsys, Guillaume worked at Mentor Graphics as a Product Marketing professional from May 2016 to March 2018. Guillaume was involved in technical marketing activities for the Veloce Power App, where they defined innovative power modeling and verification features.
Guillaume also worked at Synopsys Inc as a Sr. Staff Corporate Applications Engineer from August 2015 to April 2016. In this role, they engaged with customers, managed new features and roadmap definition for SpyGlass Power, and represented Synopsys in IEEE P2416 working group for power modeling.
From June 2012 to July 2015, Guillaume worked at Atrenta as a Sr. Technical Marketing Manager. Guillaume was involved in developing market requirements, sales strategies, and creating product collateral.
In 2011, Guillaume briefly owned and managed an online retail business called Ganda.fr, where they handled operations, sales, and marketing.
Prior to that, they worked at ST-Ericsson as a Product Manager from January 2010 to April 2011, and as a Hardware Design Project Manager from February 2009 to January 2010. In these roles, they were responsible for various managerial and technical tasks related to digital SoCs and chip design.
Guillaume began their career at STMicroelectronics as a Hardware Design Project Manager from July 2002 to February 2009, and at Thales as an RF Design Engineer from 1999 to 2002.
Guillaume Boillet's education history is as follows:
Guillaume attended Grenoble Ecole de Management from 2009 to 2012, where they obtained an MBA degree in Global Management.
From 1997 to 1998, Guillaume studied at Polytechnique Montréal and earned an MSEE degree in Telecommunications.
Guillaume also attended CentraleSupélec from 1995 to 1998, where they obtained a Diplôme d'Ingénieur degree in Telecommunications.
Prior to that, from 1993 to 1995, Guillaume attended Lycee Faidherbe and completed a Classe Préparatoire aux Grandes Ecoles with a focus on Mathématiques Spéciales M'.
In addition to their formal education, Guillaume has acquired several certifications. In 2022, they obtained the following certifications: AI Product Management Specialization from Duke University Pratt School of Engineering, Human Factors in AI from Duke University Pratt School of Engineering, Importing Data in the Tidyverse from John Hopkins University, Visualizing Data in the Tidyverse from The Johns Hopkins University, Wrangling Data in the Tidyverse from John Hopkins University, and Introduction to the Tidyverse from John Hopkins University.
Furthermore, in 2022, Guillaume also completed the certifications of Machine Learning Foundations for Product Managers and Managing Machine Learning Projects, both from Duke University Pratt School of Engineering, Customer Analytics and Operations Analytics from The Wharton School, Functional Safety Practitioner (ISO 26262) from exida, and PMC Level IV, Pragmatic Certified Product Manager, and The Business of Data Science, all from Pragmatic Institute.
Arteris
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Arteris is helping power the next wave of autonomous driving, 5G and Artificial Intelligence (AI) systems fueling the growth the of the semiconductor industry. Our Network-on-Chip (NoC) interconnect semiconductor intellectual property (IP) is the on-chip communications backbone of most of the world’s most important and sophisticated systems-on-chip(SoC). Optimizing on-chip dataflow and connectivity is the cornerstone of our vision for system-on-chip development and assembly. Since our inception in 2003, we have pioneered the development and commercialization of NoC interconnect technology, cementing our position as the world’s first and largest commercial NoC interconnect IP company. Our unique technology meets the needs for cache coherent and non-coherent on-chip communications, on-chip data caching, and on-chip data protection to meet functional safety requirements.ARTERIS IP PRODUCTS AND SOLUTIONSOur on-chip NoC-based interconnect IP products make systems-on-chip easier to develop, perform better, and faster to get to market.The Arteris IP product portfolio meets the needs of design teams creating nearly any type of digital logic SoC with any type of communications semantics. Our seminal FlexNoC® Interconnect IP pioneered the market for NoC interconnects and is the industry leader. The highly configurable Ncore® Cache Coherent Interconnect IP allows optimal integration of cache-coherent Arm®-based processor IP with other cache-coherent and non-coherent IP.The growth of Artificial Intelligence (AI) and Machine Learning (ML) has inspired the creation of two innovative products. The Arteris IP AI Package is an option to Arteris FlexNoC that provides automated means to create complex topologies (meshes, rings, and tori) while adding multicast/broadcast communications, virtual channels, and source-synchronous communications to meet the unique needs of AI/ML chips. The CodaCache® Last Level Cache provides a highly configurable cache that can be instantiated anywhere within an SoC interconnect, providing data locality wherever needed.To meet the needs of the new generation of multibillion-transistor chips for automated systems with functional safety requirements, Arteris IP also offers Resilience Packages that provide hardware-based data protection technologies as well as automated diagnostic coverage analysis to help meet requirements ISO 26262 and IEC 61508 functional standards. Resilience Packages are available for FlexNoC, Ncore and CodaCache IP products.Timing closure has become a key design schedule constraint as chips have grown in size and complexity and semiconductor manufacturing process critical dimension have shrunk. To address this, Arteris IP created the PIANO® Timing Closure Package which provides physical and timing information about the interconnect to back-end synthesis place and route tools to help ensure faster timing closure.